ARM926EJ datasheet(34/236 Pages) ETC2

34 / 236 page

Programmer’s Model

2-4

ARM DDI 0198E

All CP15 register bits that are defined and contain state are set to 0 by Reset except:

•

The V bit is set to 0 at reset if the VINITHI signal is LOW, or 1 if the VINITHI

signal is HIGH.

•

The B bit is set to 0 at reset if the BIGENDINIT signal is LOW, or 1 if the

BIGENDINIT signal is HIGH.

•

The instruction TCM is enabled at reset if the INITRAM pin is HIGH. This

enables booting from the instruction TCM and sets the ITCM bit in the ITCM

region register to 1.

2.2.1

Addresses in an ARM926EJ-S system

Three distinct types of address exist in an ARM926EJ-S system. Table 2-2 shows the

address types in ARM926EJ-S processor.

This is an example of the address manipulation that occurs when the ARM9EJ-S core

requests an instruction:

The VA of the instruction is issued by the ARM9EJ-S core.

The VA is translated using the FCSE PID value to the MVA. The Instruction

Cache (ICache) and Memory Management Unit (MMU) detect the MVA, see

Process ID Register c13 on page 2-32.

If the protection check carried out by the MMU on the MVA does not abort and

the MVA tag is in the ICache, the instruction data is returned to the ARM9EJ-S

core.

If the protection check carried out by the MMU on the MVA does not abort, and

the cache misses because the MVA tag is not in the cache, then the MMU

translates the MVA to produce the PA. This address is given to the AMBA bus

interface to perform an external access.

2.2.2

Accessing CP15 registers

You can only access CP15 registers with MRC and MCR instructions in a privileged

mode. The instruction bit pattern of the MCR and MRC instructions is shown in

Figure 2-1 on page 2-5.

Table 2-2 Address types in ARM926EJ-S

Domain

ARM9EJ-S

Caches and MMU

TCM and AMBA bus

Address type

Virtual Address (VA)

Modified Virtual Address (MVA)

Physical Address (PA)

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