ARM926EJ datasheet(73/236 Pages) ETC2

73 / 236 page

Memory Management Unit

ARM DDI 0198E

3-9

The page table descriptors provide the base address of a page table that contains

second-level descriptors. There are two sizes of page table:

•

coarse page tables have 256 entries, splitting the 1MB that the table describes into

4KB blocks

•

fine page tables have 1024 entries, splitting the 1MB that the table describes into

1KB blocks.

First-level descriptor bit assignments are shown in Table 3-2.

Table 3-2 First-level descriptor bits

Bits

Description

Section

Coarse

Fine

[31:20]

[31:10]

[31:12]

These bits form the corresponding bits of the physical

address.

[19:12]

Should Be Zero.

[11:10]

Access permission bits. Access permissions and domains on

page 3-3 and Fault address and fault status registers on

page 3-20 show how to interpret the access permission bits.

[9]

[11:9]

Should Be Zero.

[8:5]

Domain control bits.

[4]

Must be 1.

[3:2]

Bits C and B indicate whether the area of memory mapped

by this page is treated as write-back cacheable,

write-through cacheable, noncached buffered, or noncached

nonbuffered.

[3:2]

Should Be Zero.

[1:0]

These bits indicate the page size and validity and are

interpreted as shown in Table 3-3 on page 3-10.

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