ASIX ELECTRONICS CORPORATION

6

AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch

1.0 AX88655 Overview

1.1 General Description

The AX88655 Gigabit switch controller supports five 10/100/1000 Mbps ports in wire-speed operation. The AX88655

Gigabit switch controller provides five 10/100/1000 Ethernet ports with GMII/MII interface.

For each ports, the

AX88655 supports GMII (802.3ab) interface with full-duplex operation at Gigabit speed, full- or half-duplex operation

at 10/100 Mbps speed and polls the status of PHYs with an embedded MPU.

Embedded 128K bytes SRAM as a packet buffer operates with an internal 90MHz clock. For efficient utilization of the

packet buffer, there are 1024 128-byte page-links totally in the buffer.

The device supports 4K internal MAC addresses which are shared by all ports with an embedded 32K byte SSRAM. The

learning/routing engine is implemented with a two-way hash/linear algorithm to reduce possibility of routing collision.

Basically the AX88655 supports non-blocking wire speed forwarding rate and no Head-of-Line (HOL) blocking issue.

The AX88655 provides two flow-control mechanisms to avoid loss of data: an optional jamming based backpressure flow

control in the half-duplex operation and IEEE 802.3x in the full-duplex mode.

To support Quality of Service (QoS), each output port has two priority queues and their assignment can be based on the

802.1p priority field or Port-Pair setting. Each output port retrieves the frames from the shared buffer based on queuing

and sends them to the transmitting (Tx) FIFO.

1.2 AX88655 Block Diagram

Fig-1 AX88655 Block Diagram

10/100/1000 MAC

10/100/1000 MAC

10/100/1000 MAC

High Speed

Switch Fabric

Routing /Learning

Engine

Buffer Manager

Packet

Buffer

General Purpose

I/O Interface (GPIO)

GMII PHY

Address Look-up Table

10/100/1000 MAC

10/100/1000 MAC

EEPROM

Interface

GMII PHY

GMII PHY

GMII PHY

GMII PHY

GPIO

Configuration

Logic