AX88655P datasheet(8/40 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch

2.0 Pin Descriptions

2.0 I/O Definition

The following terms describe the AX88655 pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

Input

Pull Up

Output

Pull Down

I/O

Input/Output

Power Pin

Open Drain

2.1 GMII/MII Interface

2.1.1 GMII Interface Port 0

Signal Name

I/O

Pin No.

Description

GTX_CLK0

250

125MHz Clock Output: it is a continuous 125 MHz clock output to

giga-PHY operating at 1000BASE-T. That is, it is a timing reference

for TX_EN0 and TXD0[7:0]

TX_EN0

Transmit Enable: When TX_EN0 is asserted, data on TXD0[7:0] are

transmitted onto PHY. TX_EN0 is synchronous to GTX_CLK0 in

1000BASE-T mode and synchronous to TX_CLK0 in 10/100BASE-T

mode.

TXD0[7:0]

4 – 1,

256 – 253

Transmit Data: Synchronous to the rising of GTX_CLK0 in

1000BASE-T mode. And synchronous to rising edge of TX_CLK0 in

10/100BASE-T mode.

TX_CLK0

I/PD

252

MII

Transmit

Clock

Input:

TX_EN0

and

TXD0[3:0]

are

synchronous to the rising edge of this clock in 10/100BASE-T mode.

COL0

I/PD

238

Collision Detect: Active high to indicate that there is collision

occurred in half duplex mode. In full duplex mode COL0 is always low.

CRS0

I/PD

237

Carrier Sense: Active high if there is carrier on medium. In half

duplex mode CRS0 is also asserted during transmission and

asynchronous to any clock.

RX_DV0

248

Receive Data Valid: Active high to indicate that data presented on

RXD0[7:0] is valid and synchronous to RX_CLK0.

RX_CLK0

247

Receive Clock Input: 125, 25 and 2.5 MHz is running at 1000/100/10

BASE-T mode respectively. RX_DV0 and RXD0[7:0] are synchronous

to rising edge of this clock.

RXD0[7:0]

I/PD

246 - 239

Receive Data: Data received by the PHY are presented on RXD0 and

synchronous

RX_CLK0.

RXD0[3:0]

valid

10/100/1000BASE-T and RXD[7:4] is valid only in 1000BASE-T

modes.

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