HD64F2145 datasheet(447/829 Pages) RENESAS

447 / 829 page

Rev. 2.0, 08/02, page 407 of 788

Bit

Bit Name

Initial Value R/W

Description

IRIC

R/W

2C Bus Interface Interrupt Request Flag

Indicates that the I

2C bus interface has issued an interrupt

request to the CPU.

IRIC is set at different times depending on the FS bit in

SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See

section 16.4.7, IRIC Setting Timing and SCL Control. The

conditions under which IRIC is set also differ depending on

the setting of the ACKE bit in ICCR.

[Setting conditions]

2C bus format master mode:

• When a start condition is detected in the bus line state

after a start condition is issued (when the ICDRE flag is

set to 1 because of first frame transmission)

• When a wait is inserted between the data and

acknowledge bit when the WAIT bit is 1 (fall of the 8th

transmit/receive clock)

• At the end of data transfer (rise of the 9th

transmit/receive clock while no wait is inserted)

• When a slave address is received after bus arbitration

is lost (the first frame after the start condition)

• If 1 is received as the acknowledge bit (when the ACKB

bit in ICSR is set to 1) when the ACKE bit is 1

• When the AL flag is set to 1 after bus arbitration is lost

while the ALIE bit is 1

2C bus format slave mode:

• When the slave address (SVA or SVAX) matches

(when the AAS or AASX flag in ICSR is set to 1) and at

the end of data transfer up to the subsequent

retransmission start condition or stop condition

detection (rise of the 9th transmit/receive clock)

• When the general call address is detected (when 0 is

received as the R/

: bit and the ADZ flag in ICSR is set

to 1) and at the end of data reception up to the

subsequent retransmission start condition or stop

condition detection (rise of the 9th receive clock)

• If 1 is received as the acknowledge bit (when the ACKB

bit in ICSR is set to 1) while the ACKE bit is 1

• When a stop condition is detected (when the STOP or

ESTP flag in ICSR is set to 1) while the STOPIM bit is 0

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