HD64F2145 datasheet(445/829 Pages) RENESAS

445 / 829 page

Rev. 2.0, 08/02, page 405 of 788

Bit

Bit Name

Initial Value R/W

Description

MST

TRS

R/W

[MST clearing conditions]

1. When 0 is written by software

2. When lost in bus contention in I

2C bus format master

mode

[MST setting conditions]

1. When 1 is written by software (for MST clearing

condition 1)

2. When 1 is written in MST after reading MST = 0 (for

MST clearing condition 2)

[TRS clearing conditions]

1. When 0 is written by software (except for TRS setting

condition 3)

2. When 0 is written in TRS after reading TRS = 1 (for

TRS setting condition 3)

When lost in bus contention in I

2C bus format master

mode

4. When the SW bit in DDCSWR is changed from 1 to 0

[TRS setting conditions]

1. When 1 is written by software (except for TRS clearing

conditions 3 and 4)

2. When 1 is written in TRS after reading TRS = 0 (for

TRS clearing conditions 3 and 4)

3. When 1 is received as the R/

: bit after the first frame

address matching in I

2C bus format slave mode

ACKE

R/W

Acknowledge Bit Decision and Selection

0: The value of the acknowledge bit is ignored, and

continuous transfer is performed. The value of the

received acknowledge bit is not indicated by the ACKB

bit in ICSR, which is always 0.

1: If the received acknowledge bit is 1, continuous transfer

is halted.

Depending on the receiving device, the acknowledge bit

may be significant, in indicating completion of processing of

the received data, for instance, or may be fixed at 1 and

have no significance.

HD64F2145 Datasheet(PDF) 445 Page - Renesas Technology Corp

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