HD64F2145 datasheet(444/829 Pages) RENESAS

444 / 829 page

Rev. 2.0, 08/02, page 404 of 788

16.3.5

2C Bus Control Register (ICCR)

ICCR controls the I

2C bus interface and performs interrupt flag confirmation.

Bit

Bit Name

Initial Value R/W

Description

7ICE

R/W

2C Bus Interface Enable

0: I

2C bus interface modules are stopped and I2C bus

interface module internal state is initialized. SAR and SARX

can be accessed.

1: I

2C bus interface modules can perform transfer

operation, and the ports function as the SCL and SDA

input/output pins. ICMR and ICDR can be accessed.

6IEIC

R/W

2C Bus Interface Interrupt Enable

0: Disables interrupts from the I

2C bus interface to the CPU

1: Enables interrupts from the I

2C bus interface to the CPU.

MST

TRS

R/W

Master/Slave Select

Transmit/Receive Select

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

Both these bits will be cleared by hardware when they lose

in a bus contention in master mode with the I

2C bus format.

In slave receive mode with I

2C bus format, the R/W bit in

the first frame immediately after the start condition sets

these bits in receive mode or transmit mode automatically

by hardware.

Modification of the TRS bit during transfer is deferred until

transfer is completed, and the changeover is made after

completion of the transfer.

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