PCI6621 datasheet(67/204 Pages) TI

67 / 204 page

3−19

The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).

These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−12 describes the SMI control

bits function.

Table 3−12. SMI Control

BIT NAME

FUNCTION

SMIROUTE

This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.

SMISTAT

This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.

SMIENB

When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.

If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt

can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset

1Eh/5Eh/81Eh, see Section 5.20).

If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data

slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either

MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.36).

3.8

Power Management Overview

In addition to the low-power CMOS technology process used for the PCI6x21/PCI6x11 controller, various features

are designed into the controller to allow implementation of popular power-saving techniques. These features and

techniques are as follows:

•

Clock run protocol

•

Cardbus PC Card power management

•

16-bit PC Card power management

•

Suspend mode

•

Ring indicate

•

PCI power management

•

Cardbus bridge power management

•

ACPI support

PCI6621 Datasheet(PDF) 67 Page - Texas Instruments