CS8920A datasheet(29/144 Pages) CIRRUS

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Transmit Error Detection and Handling

The MAC engine monitors Ethernet activity and

reports and recovers from a number of error con-

ditions. For transmission, the MAC reports the

following errors in the TxEvent register (Register

8) and BufEvent register (Register C):

Loss of Carrier: Whenever the CS8920A is

transmitting on the AUI port, it expects to see its

own transmission "looped back" to its receiver. If

it is unable to monitor its transmission after the

end of the preamble, the MAC reports a loss-of-

carrier error by setting the Loss-of-CRS bit

(Register 8, TxEvent, Bit 6). If the Loss-of-

CRSiE bit (Register 7, TxCFG, Bit 6) is set, the

host will be interrupted.

SQE Error: After the end of transmission on the

AUI port, the MAC expects to see a collision

within 64 bit times. If no collision is detected,

the SQEerror bit (Register 8, TxEvent, Bit 7) is

set. If the SQEerroriE bit is set (Register 7,

TxCFG, Bit 7), the host is interrupted. An SQE

error may indicate a fault on the AUI cable or a

faulty transceiver (it is assumed that the attached

transceiver supports this function).

Out-of-Window (Late) Collision: If a collision is

detected after the first 512 bits have been trans-

mitted, the MAC reports a late collision by

setting the Out-of-window bit (Register 8,

TxEvent, Bit 9). The MAC then forces a bad

CRC and terminates the transmission. If the Out-

of-windowiE bit (Register 7, TxCFG, Bit 9) is

set, the host is interrupted. A late collision may

indicate an illegal network configuration.

Jabber Error: If a transmission continues longer

than about 26 ms, the MAC disables the trans-

mitter and sets the Jabber bit (Register 8,

TxEvent, Bit A). The output of the transmitter

returns to idle and remains there until the host

issues a new Transmit Command. If the JabberiE

bit (Register 7, TxCFG, Bit A) is set, the host is

interrupted. A Jabber condition indicates that

t here may be so me thi ng wrong with the

CS8920A transmit function. To prevent possible

network faults, the host should clear the transmit

buffer. Possible options include:

Reset the chip with either software or hardware

reset (see Section 3.3).

Issue a Force Transmit Command by setting the

Force bit (Register 9, TxCMD, bit 8).

Issue a Transmit Command with the TxLength

field set to zero.

Transmit Collision: The MAC counts the num-

ber of times an individual packet must be

re-transmitted due to network collisions. The col-

lision count is stored in bits B through E of the

TxEvent register (Register 8). If the packet col-

lides 16 times, transmission of that packet is

terminated and the 16coll bit (Register 8,

TxEvent, Bit F) is set. If the 16colliE bit (Regis-

ter 7, TxCFG, Bit F) is set, the host will be

interrupted on the 16th collision. A running

count of transmit collisions is recorded in the

TxCOL register.

Transmit Underrun: If the CS8920A starts

transmission of a packet but runs out of data be-

fore reaching the end of frame, the TxUnderrun

bit (Register C, BufEvent, Bit 9) is set. The

MAC then forces a bad CRC and terminates the

transmission. If the TxUnderruniE bit (Register

B, BufCFG, Bit 9) is set, the host is interrupted.

Receive Error Detection and Handling

The following receive errors are reported in the

RxEvent register (Register 4):

CRC Error: If a frame is received with a bad

CRC, the CRCerror bit (Register 4, RxEvent, Bit

C) is set. If the CRCerrorA bit (Register 5,

RxCTL, Bit C) is set, the frame will be buffered

by the CS8920A. If the CRCerroriE bit (Register

3, RxCFG. Bit C) is set, the host is interrupted.

CS8920A

DS238PP2

CS8920A Datasheet(PDF) 29 Page - Cirrus Logic

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