uP9511

6

uP9511-DS-C3100, Feb. 2016

www.upi-semi.com

Functional Description

Power On Reset (POR)

Figure 1 shows the power ready detection circuit. The 5VCC

voltage is monitored for power on reset with typically 4.3V

threshold at its rising edge. When 5VCC is ready, the

controller waits for EN to start up. When EN pin is driven

above 0.4V, the controller begins its start up sequence.

When EN pin is driven below 0.2V, the controller will be

turned off, and it will clear all fault states to prepare to next

soft-start once the controller is re-enabled.

5VCC

EN

4.3V

0.4V

POR

Figure 1. Circuit of Power Ready Detection

Power Input Monitor

VINMON is the power stage input voltage sense pin.

Connect this pin to power stage input voltage (VIN) with a

voltage divider and always keep VINMON of power stage

input voltage. When VINMON less than typically 0.5V at

POR, the uP9511 will forces starts up at single phase and

disables the cold boot, warm boot, PSI and auto-phase

function. Once this condition is triggered, it can only be

reset by re-POR or EN restart.

Phase Number of Operation (Hardware Programming)

The uP9511 supports 8/7/6/5/4/3/2/1-phase operation. The

maximum phase number of operation is determined by

checking the status of ISENx pins when power on reset.

Normally, uP9511 is 8-phase operation. Pull ISEN8 to 5VCC

with a 100k

Ω for 7-phase operation; Pull ISEN7 to 5VCC

with a 100k

Ω for 6-phase operation and so on. When

operating in 7-phase, PWM8 outputs are set to high

impedance; in 6-phase, PWM[8:7] outputs are set to high

impedance and so on. The maximum phase number of

operation is decided and latched at each POR rising edge.

The unused ISENx pins and PWMx pins can be left floating.

Operation Frequency

The phase switching frequency of the uP9511 is set by an

external resistor connected between PROG6 pin and GND.

Table 1 lists the operation frequency and the recommended

resistor R

Table 1. Operation Frequency and Recommended R

PROG6

y

c

n

e

u

q

e

r

F

g

n

i

h

c

t

i

w

S

)

z

H

k

(

R

d

e

d

n

e

m

m

o

c

e

R

6

G

O

R

P

r

o

t

s

i

s

e

R

k

(

Ω)

0

0

21

5

0

0

33

3

0

0

44

2

0

0

50

2

0

0

66

1

Power Saving Mode

The uP9511 provides power saving features for platform

designers to program platform specific power saving

configuration. There are three operation modes: Full-Phase

mode, Auto-Phase mode, and Low-Phase mode. The

uP9511 switches between these three operation modes

according to the input voltage level of the PSI pin. Figure 2

shows typical PSI application circuit, and table 2 shows

recommended PSI setting voltage level of three operation

modes. In low-phase mode, it can separate into Cold Boot

Mode and Warm Boot Mode. The operation phase number

of Cold Boot Mode and Warm Boot Mode is determined by

will auto increasing/reducing according to output loading.

operation is determined by checking the status of ISENx

pins when POR.

PSI

Power State

Selection

1.8V

H-L Logic

Figure 2. PSI application circuit

Table 2. Operation Mode and recommended V

PSI

e

d

o

M

n

o

i

t

a

r

e

p

O

g

n

i

t

t

e

S

e

g

a

t

l

o

V

d

e

d

n

e

m

m

o

c

e

R

I

S

P

t

a

e

d

o

M

e

s

a

h

P

-

ll

u

FV

8

.

1

e

d

o

M

e

s

a

h

P

-

o

t

u

AV

1

e

d

o

M

e

s

a

h

P

-

w

o

LD

N

G

Auto-Phase Shedding

The uP9511 provide Auto-Phase Shedding function to reduce

the switching and conduction losses at light load condition

and enable high efficiency over a wide range of output current.

Auto-Phase Shedding function is activated by two conditions:

1. PSI voltage stays at “Auto-Phase Mode”.

2. After PGOOD goes high, VID pin received the PWM-VID

input signal from GPU.

uP9511 compares the V

V

Connect each PROGx pins to 5VCC with a voltage divider

to set the threshold and hysteresis. The threshold and the

hysteresis can be calculated as:

6

.

0

5

+

×

⎟⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎝

⎛

×

=

×

+

=

IMON

SUM

DC

OUT

CC

BOT

TOP

BOT

PROGx

R

R

N

R

I

V

R

R

R

V