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M58LT128GS Datasheet(PDF) 23 Page - STMicroelectronics |
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M58LT128GS Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 98 page ![]() M58LT128GST, M58LT128GSB 4 Command Interface 23/98 4.9 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: ● The targeted block must be unprotected. if it is protected, the user must return the device to read mode. ● VPP must be set to VPPH. ● VDD must be within operating range. ● Ambient temperature TA must be 30°C ± 10°C. ● The start address must be aligned with the start of a 32 Word buffer boundary. ● The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, See Appendix C, Figure 25: Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command and to Table 6: Factory Program Command for details on the Buffer Enhanced Factory Program command. 4.9.1 Setup phase The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command. 1. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. 2. The second Bus Write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error. |
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