ADAV801ASTZ datasheet(31/56 Pages) AD

31 / 56 page

ADAV801

Rev. 0 | Page 31 of 56

IV1

IV0

DIV1

Table 17. SRC and Clock Control Registe

SRCD

CLK2

CLK2DIV0

CLK1DIV1

CLK1DIV0

MCLKSEL1

MCLKSEL0

ADDRESS = 0000000 (0x00)

SRCDIV1–0

Divides the SRC master clock.

00 = SRC master clock is not divided.

vided by 1.5.

is divided by 2.

is divided by 3.

e by 1.5.

ck 1 (ICLK1).

01 = Divide by 1.5.

10 = Divide by 2.

selection

e SRC m

= Internal C

k 1.

ernal Clock 2.

6 × fS).

01 = SRC master clock is di

10 = SRC master clock

11= SRC master clock

CLK2DIV1–0

Clock divider for Internal Clock 2 (ICLK2).

00 = Divide by 1.

01 = Divid

10 = Divide by 2.

11 = Divide by 3.

CLK1DIV1–0

Clock divider for Internal Clo

00 = Divide by 1.

11 = Divide by 3.

MCLKSEL1–0

Clock

for th

aster clock.

loc

01 = Int

10 = PLL recovered clock (512 × fS).

11 = PLL recovered clock (25

Table 18. SPDIF Loop

RES

TxMUX

back Control Register

RES

ADDRESS = 0000011 (0x03)

TxMUX

Selects the source for SPDIF output (DITOUT).

0 = SPDIF transmitter, normal mode.

1 = DIRIN, loopback mode.

Table 19. Playback Port Control Register

CLKSRC0

SPMODE2

SPMODE1

SPMODE0

RES

CLKSRC1

ADDRESS = 0000100 (0x04)

CLKSRC1–0

Selects the clock source for generating the ILRCLK and IBCLK.

00 = Input port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE2–0

Selects the serial format of the playback port.

000 = Left-justified.

001 = I2S.

100 = 24-bit, right-justified.

101 = 20-bit, right-justified.

110 = 18-bit, right-justified.

111 = 16-bit, right-justified.

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