ADAV801ASTZ datasheet(22/56 Pages) AD

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ADAV801

Rev. 0 | Page 22 of 56

an external

PLL SECTION

The ADAV801 features a dual PLL configuration to generate

independent system clocks for asynchronous operation.

Figure 37 shows the block diagram of the PLL section. The PLL

generates the internal and system clocks from a 27 MHz clock.

This clock is generated either by a crystal connected between

XIN and XOUT, as shown in Figure 35, or from

clock source connected directly to XIN. A 54 MHz clock can

also be used, if the internal clock divider is used.

XTAL

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently

and can accommodate a range of sampling rates (32/44.1/48

kHz) with selectable system clock oversampling rates of 256 and

384. Higher oversampling rates can also be selected by enabling

the doubling of the sampling rate to give 512 or 768 × fS ratios.

Note that this option also allows oversampling ratios of 256 or

384 at double sample r

The PLL outputs can be routed internally to act as clock sources

for the oth

, and so

on. The outputs of the PLLs are also available on the three

SYSCLK pins. Figure 38 shows how the PLLs can be configured

to provide the sampling clocks.

MCLK Selection

ates of 64/88.2/96 kH

er component blocks such as the ADC, DAC

Table 7. PLL Frequency Selection Options

PLL

Sample Rate (fS)

Normal fS

Double fS

32/44.1/48 kHz

256/384 × fS

512/768 × fS

64/88.2/96 kHz

256/384 × fS

32/44.1/48 kHz

256/384 × fS

512/768 × fS

64/88.2/96 kHz

256/384 × fS

Same as fS selected

512 × fS

For PLL 2A

512 × fS

The PLLs require some external components to operate

correctly. These c

6, form a loop

p and

ows

d as master clocks

r t

e ADAV801

e DAC or ADC.

nd gro

pins, which should be

t electri

se from being

ouplin

ns.

omponents, shown in Figure 3

filter that integrates the current pulses from a charge pum

produces a voltage that is used to tune the VCO. Good quali

capacitors, such as PPS film, are recommended. Figure 37 sh

a block diagram of the PLL section, including master clock

selection. Figure 38 shows how the clock frequencies at the

clock output pins, SYSCLK1 to SYSCLK 3, and the internal PLL

clock values, PLL1 and PLL2, are selected.

The clock nodes, PLL1 and PLL2, can be use

fo he other blocks in th

such as th

Th PLL has separate supply a

und

as c ean as possible to preven

cal noi

co erted into clock jitter by c

g onto the loop filter pi

PLL BLOCK

3.3k

Ω

PLL_LFx

100nF

AVDD

6.8nF

Figure 36. PLL Loop Filter

MCLKI

REG 0x

BIT

MCLKO

REG 0x74

BIT 5

G 0x74

BIT 4

REG 0x78

BIT 6

PHASE

DETECTOR

AND LOOP

FILTER

PLL1

SYSCLK1

SYSCLK2

SYSCLK3

PLL_LF2

XOUT

XIN

PLL_LF1

÷2

VCO

÷N

OUTPUT

SCALER N1

PHASE

DETECTOR

AND LOOP

FILTER

PLL2

VCO

÷N

OUTPUT

SCALER N2

OUTPUT

SCALER N3

Section Block Diagram

Figure 37. PLL

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