ADAV801ASTZ datasheet(28/56 Pages) AD

28 / 56 page

ADAV801

Rev. 0 | Page 28 of 56

REG 0x76

BITS 4–2

DIR PLL (512 ×

fS)

DIR PLL (256 ×

fS)

PLLINT1

PLLINT2

MCLKI

XIN

ICLK1

ICLK2

PLL CLOCK

REG 0x06

BITS 4–3

MCLK

ADC

OUTPUT

PORT

OLRCLK

OBC

OSDATA

REG 0x76

BITS 7–5

DIR PLL (512 ×

fS)

DIR PLL (256 ×

fS)

PLLINT1

PLLINT2

MCLKI

XIN

ICLK1

ICLK2

PLL CLOCK

REG 0x04

BITS 4-3

MCLK

DAC

INPUT

PORT

ILRCLK

IBCLK

ISDATA

REG 0x77

BITS 4–3

REG 0x00

BITS 3–2

REG 0x00

BITS 1–0

REG 0x00

BITS 4–5

REG 0x76

BITS 1–0

MCLKI

XIN

PLLINT1

PLLINT2

ICLK1

ICLK2

DIR PLL (512 ×

fS)

DIR PLL (256 ×

fS)

REG 0x00

BITS 1-0

MCLKI

XIN

PLLINT1

PLLINT2

DIVIDER

SRC

MCLK

Figure 50. SPORT Clocking Scheme

le,

MCLKI input to ensure that the

C and serial port are

synchronized.

The SPORTs can be set

ive data in I2S, left-

justified or right-justified formats with different word lengths

by programming the appropriate bits in the playback register,

auxiliary input port register, record register, and auxiliary

output port-control register. Figure 51 is a timing diagram of

the serial data port formats.

Clocking Scheme

The ADAV801 provides a flexible choice of on-chip and off-

chip clocking sources. The on-chip oscillator with dual PLLs is

intended to offer complete system clocking requirements for

use with available MPEG encoders, decoders, or a combination

of codecs. The oscillator function is designed for generation of a

27 MHz video clock from a 27 MHz crystal connected between

the XIN and XOUT pins. Capacitors must also be connected

between these pins and DGND, as shown in Figure 35. The

capacitor values should be specified by the crystal manufacturer.

A square wave version of the crystal clock is output on the

MCLKO pin. If the system has a 27 MHz clock available, this

clock can be connected directly to the XIN pin.

Care should be taken to ensure that the clock rate is appropriate

for whatever block is connected to the serial port. For examp

if the ADC is running from the MCLKI input at 256 × fS, then

the master clock for the SPORT should also run from the

to transmit or rece

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LSB

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL

I2S MODE — 16 BITS TO 24 BITS PER CHANNEL

LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL

Figure 51. Serial Data Modes

ADAV801ASTZ Datasheet(PDF) 28 Page - Analog Devices

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