ADAV801ASTZ datasheet(15/56 Pages) AD

15 / 56 page

ADAV801

Rev. 0 | Page 15 of 56

TION

and by a factor of 8 at

ther the

FUNCTIONAL DESCRIP

ADC SECTION

The ADAV801’s ADC section is implemented using a second-

order multibit (5 bits) Σ-∆ modulator. The modulator is

sampled at either half of the ADC MCLK rate (modulator clo

= 128 × fS) or one-quarter of the ADC MCLK rate (modulator

clock = 64 × fS). The digital decimator consists of a Sinc^5 filter

followed by a cascade of three half-band FIR filters. The Sin

decimates by a factor of 16 at 48 kHz

96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. The ADC can

be clocked by a number of different clock sources to control t

sample rate. MCLK selection for the ADC is set by Internal

Clocking Control Register 1 (Address 0x76). The ADC provide

an output word of up to 24 bits in resolution in twos comple-

ment format. The output word can be routed to ei

output ports, the sample rate converter, or the SPDIF digital

transmitter.

REG 0x76

BITS 4–2

REG 0x6F

BITS 1–0

ADC MCLK

DIVIDER

ADC

MCLK

ADC

Figure 23. Clock Path Control on the ADC

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts

the single-ended signal to a differential signal, which is applied

to the analog Σ-Δ modulator of the ADC. The PGA can be

programmed to amplify a signal by up to 24 dB in 0.5 dB

increments. Figure 24 shows the structure of the PGA circuit.

Ω TO 64kΩ

125

Ω

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

VREF

MODULATOR

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

EXTERNAL

CAPACITOR

(1nF NPO)

Ω

125

Ω

Figure 24. PGA Block Diagram

Analog Σ-∆ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The

input features two integrators in cascade followed by a flash

converter. This multibit output is directed to a scrambler,

followed by a DAC for loop feedback. The flash ADC outp

also converted from thermometer coding to binary codin

input as a 5-bit word to the decimator. F

ut is

g for

igure 25 shows the

ADC block diagram.

The ADC also features independent digital volume control for

the left and right channels. The volume control consists of

256 linear steps, with each step reducing the digital output

codes by 0.39%. Each channel also has a peak detector that

records the peak level of the input signal. The peak detector

ADC MCLK

AMC

(REG 0X63

BIT-7)

MULTIBIT

Σ–∆

MODULATOR

DECIMATOR

HPF

PEAK

DETECT

VOLUME

ONTROL

SINC^5

HALF-BAND

FILTER

MODULATOR

CLOCK

(6.144MHz MAX)

384kHz

768kHz

SINC

COMPENSATION

192kHz

384kHz

HALF-BAND

FILTER

96kHz

192kHz

48kHz

96kHz

÷2

÷4

Diagram

Figure 25. ADC Block

ADAV801ASTZ Datasheet(PDF) 15 Page - Analog Devices

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