ESP32 datasheet(25/64 Pages) ESPRESSIF

25 / 64 page

3. Functional Description

Category

Target

Start Address

End Address

Size

Peripheral

SPI2

0x3FF6_4000

0x3FF6_4FFF

4 KB

SPI3

0x3FF6_5000

0x3FF6_5FFF

4 KB

SYSCON

0x3FF6_6000

0x3FF6_6FFF

4 KB

I2C1

0x3FF6_7000

0x3FF6_7FFF

4 KB

SDMMC

0x3FF6_8000

0x3FF6_8FFF

4 KB

EMAC

0x3FF6_9000

0x3FF6_AFFF

8 KB

PWM1

0x3FF6_C000

0x3FF6_CFFF

4 KB

I2S1

0x3FF6_D000

0x3FF6_DFFF

4 KB

UART2

0x3FF6_E000

0x3FF6_EFFF

4 KB

PWM2

0x3FF6_F000

0x3FF6_FFFF

4 KB

PWM3

0x3FF7_0000

0x3FF7_0FFF

4 KB

RNG

0x3FF7_5000

0x3FF7_5FFF

4 KB

3.2 Timers and Watchdogs

3.2.1 64-bit Timers

There are four general-purpose timers embedded in the chip. They are all 64-bit generic timers which are based

on 16-bit prescalers and 64-bit auto-reload-capable up/down-timers.

The timers feature:

• A 16-bit clock prescaler, from 2 to 65536

• A 64-bit timer

• Configurable up/down timer: incrementing or decrementing

• Halt and resume of time-base counter

• Auto-reload at alarming

• Software-controlled instant reload

• Level and edge interrupt generation

3.2.2 Watchdog Timers

The chip has three watchdog timers: one in each of the two timer modules (called the Main Watchdog Timer,

or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). These watchdog timers are

intended to recover from an unforeseen fault causing the application program to abandon its normal sequence. A

watchdog timer has four stages. Each stage may trigger one of three or four possible actions upon the expiry of

its programmed time period, unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, core

reset, and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip, including

the RTC itself. A timeout value can be set for each stage individually.

During flash boot the RWDT and the first MWDT start automatically in order to detect, and recover from, booting

problems.

The watchdogs have the following features:

• Four stages, each of which can be configured or disabled separately

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