ESP32 datasheet(43/64 Pages) ESPRESSIF

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5. Electrical Characteristics

5.3 DC Characteristics (3.3 V, 25 °C)

Table 13: DC Characteristics (3.3 V, 25 °C)

Symbol

Parameter

Min

Typ

Max

Unit

CIN

Pin capacitance

VIH

High-level input voltage

0.75×VDD1

VDD1+0.3

VIL

Low-level input voltage

–0.3

0.25×VDD1

IIH

High-level input current

IIL

Low-level input current

VOH

High-level output voltage

0.8×VDD1

VOL

Low-level output voltage

0.1×VDD1

IOH

High-level source current

(VDD1 = 3.3 V,

VOH >= 2.64 V,

output drive strength set

to the maximum)

VDD3P3_CPU

power domain 1, 2

VDD3P3_RTC

power domain 1, 2

VDD_SDIO power

domain 1, 3

IOL

Low-level sink current

(VDD1 = 3.3 V, VOL = 0.495 V,

output drive strength set to the maximum)

RP U

Resistance of internal pull-up resistor

kΩ

RP D

Resistance of internal pull-down resistor

kΩ

VIL_nRST

Low-level input voltage of CHIP_PU

to power off the chip

0.6

Notes:

1. Please see Table IO_MUX for IO’s power domain. VDD is the I/O voltage for a particular power domain of pins.

2. For VDD3P3_CPU and VDD3P3_RTC power domain, per-pin current sourced in the same domain is gradually reduced

from around 40 mA to around 29 mA, VOH >=2.64 V, as the number of current-source pins increases.

3. For VDD_SDIO power domain, per-pin current sourced in the same domain is gradually reduced from around 30 mA to

around 10 mA, VOH >=2.64 V, as the number of current-source pins increases.

5.4 Reliability Qualifications

Table 14: Reliability Qualifications

Reliability tests

Standards

Test conditions

Result

Electro-Static Discharge Sensitivity

(ESD), Charge Device Mode (CDM) 1

JEDEC EIA/JESD22-C101

±500 V, all pins

Pass

Electro-Static Discharge Sensitivity

(ESD), Human Body Mode (HBM) 2

JEDEC EIA/JESD22-A114

±1500 V, all pins

Pass

Latch-up (Over-current test)

JEDEC STANDARD NO.78

±50 mA

~ ±200 mA, room

temperature, test for IO

Pass

Latch-up (Over-voltage test)

JEDEC STANDARD NO.78

1.5 × Vmax, room temper-

ature, test for Vsupply

Pass

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