SAMD21J datasheet(27/59 Pages) MICROCHIP

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(INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the

peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s

Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the

peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the

peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests

for one peripheral are ORed together on system level, generating one interrupt request for each

peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt

pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it

must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC

interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

Table 7-3. Interrupt Line Mapping

Peripheral Source

NVIC Line

EIC NMI – External Interrupt Controller

NMI

PM – Power Manager

SYSCTRL – System Control

WDT – Watchdog Timer

RTC – Real Time Counter

EIC – External Interrupt Controller

NVMCTRL – Non-Volatile Memory Controller

DMAC - Direct Memory Access Controller

USB - Universal Serial Bus

EVSYS – Event System

SERCOM0 – Serial Communication Interface 0

SERCOM1 – Serial Communication Interface 1

SERCOM2 – Serial Communication Interface 2

SERCOM3 – Serial Communication Interface 3

SERCOM4 – Serial Communication Interface 4

SERCOM5 – Serial Communication Interface 5

TCC0 – Timer Counter for Control 0

TCC1 – Timer Counter for Control 1

TCC2 – Timer Counter for Control 2

TC3 – Timer Counter 3

TC4 – Timer Counter 4

TC5 – Timer Counter 5

TC6 – Timer Counter 6

TC7 – Timer Counter 7

ADC – Analog-to-Digital Converter

32-bit ARM-Based Microcontrollers

Datasheet Summary

40001884A-page 27

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