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SAMD21J Datasheet(PDF) 29 Page - Microchip Technology |
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SAMD21J Datasheet(HTML) 29 Page - Microchip Technology |
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29 / 59 page ![]() 7.4 High-Speed Bus System 7.4.1 Features High-Speed Bus Matrix has the following features: • Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves • 32-bit data bus • Operation at a one-to-one clock frequency with the bus masters 7.4.2 Configuration CM0+ 0 DSU 1 High-Speed Bus SLAVES 0 1 2 3 4 6 SRAM DSU 1 MTB USB DMAC WB DMAC Fetch DSU 2 DMAC Data 4 5 0 1 2 3 6 5 SLAVE ID SRAM PORT ID MASTER ID Table 7-4. Bus Matrix Masters Bus Matrix Masters Master ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 32-bit ARM-Based Microcontrollers © 2017 Microchip Technology Inc. Datasheet Summary 40001884A-page 29 |
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