T1024 datasheet(35/49 Pages) FREESCALE

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Chapter 3

CPLD Specification

This section explains the CPLD registers.

3.1 CPLD Memory Map/Register Definition

The table below shows the memory map for CPLD registers.

CPLD memory map

Offset

address

(hex)

Width

(in bits)

Access Reset value

Section/

page

Chip ID1 Register (CPLD_CHIPID1)

55h

3.1.1/36

Chip ID2 Register (CPLD_CHIPID2)

AAh

3.1.2/36

Hardware Version Register (CPLD_HWVER)

See section

3.1.3/36

Software Version Register (CPLD_SWVER)

See section

3.1.4/37

Reset Control Register (CPLD_RSTCON)

w1c

00h

3.1.5/37

Reset Control Register (CPLD_RSTCON2)

w1c

00h

3.1.6/38

Interrupt Status Register (CPLD_INTSR)

00h

3.1.7/39

Flash Control and Status Register (CPLD_FLHCSR)

R/W

See section

3.1.8/40

Fan Control and Status Register (CPLD_FANCSR)

R/W

0Fh

3.1.9/40

Panel LED Control and Status Register (CPLD_LEDCSR)

R/W

00h

3.1.10/41

SDHC Card Status Register (CPLD_SDSR)

See section

3.1.11/41

Miscellanies Control and Status Register (CPLD_MISCCSR)

R/W

See section

3.1.12/42

Boot Configuration Override Register (CPLD_BOOTOR)

R/W

00h

3.1.13/42

Boot Configuration Register 1 (CPLD_BOOTCFG1)

R/W

00h

3.1.14/43

Boot Configuration Register 2 (CPLD_BOOTCFG2)

R/W

00h

3.1.15/43

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

T1024 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

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