T1024 datasheet(38/49 Pages) FREESCALE

38 / 49 page

CPLD_RSTCON field descriptions (continued)

Field

Description

4–5

This field is reserved.

XGT1_RST

No reset occurs.

Write a logic 1 will produce 10G BASE-T PHY(AQR105) reset# signal, this bit can auto clear.

XGT2_RST

No reset occurs.

Write a logic 1 will produce 2.5G SGMII PHY(AQR105) reset# signal, this bit can auto clear.

3.1.6 Reset Control Register (CPLD_RSTCON2 )

Address: 0h base + 11h offset = 11h

Bit

Read

Reserved

TDMR_RST

PEX_RST

MPEX1_

RST

MPEX2_

RST

Write

w1c

Reset

CPLD_RSTCON2 field descriptions

Field

Description

0–3

This field is reserved.

TDMR_RST

No reset occurs.

Write a logic 1 will produce TDM riser card reset# signal, this bit can auto clear.

PEX_RST

No reset occurs.

Write a logic 1 will produce PCIe x4 slot reset# signal, this bit can auto clear.

MPEX1_RST

No reset occurs.

Write a logic 1 will produce miniPCIe card1 reset# signal, this bit can auto clear.

MPEX2_RST

No reset occurs.

Write a logic 1 will produce miniPCIe card2 reset# signal, this bit can auto clear.

CPLD Memory Map/Register Definition

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

T1024 Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

T1024 Datasheet(HTML) 38 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL