T1024 datasheet(42/49 Pages) FREESCALE

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3.1.12 Miscellanies Control and Status Register

(CPLD_MISCCSR)

Address: 0h base + 17h offset = 17h

Bit

Read

Reserved

SLEEP_EN

REQ_MD

TDMR_PRS

PEX_PRS

Reserved

TEST_SEL_

Write

Reset

* Notes:

x depends on whether TDM or PCIe card is plugged in.x = Undefined at reset.

•

CPLD_MISCCSR field descriptions

Field

Description

This field is reserved.

SLEEP_EN

Deep sleep enable bit

Normal operation.

Before enter deep sleep mode, set ‘1’ to this bit, after exit deep sleep mode, set ‘0’ to this bit.

2–3

REQ_MD

No reset occurs when HRESET_REQ triggered.

HRESET occurs when HRESET_REQ triggered.

PORESET occurs when HRESET_REQ triggered.

TDMR_PRS

TDM riser card not present.

TDM riser card present.

PEX_PRS

PCIe x1 card not present.

PCIe x1 card present.

This field is reserved.

TEST_SEL_N

TEST_SEL_N pin status is 0.

TEST_SEL_N pin status is 1.

3.1.13 Boot Configuration Override Register (CPLD_BOOTOR)

Address: 0h base + 18h offset = 18h

Bit

Read

Reserved

Write

Reset

Bit

Read

Reserved

PCIE_2.5G_OR

BOOT_OR

Write

Reset

CPLD Memory Map/Register Definition

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

T1024 Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc

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