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CS47L15 Datasheet(PDF) 7 Page - Cirrus Logic |
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CS47L15 Datasheet(HTML) 7 Page - Cirrus Logic |
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7 / 279 page ![]() 7 DS1137F2 CS47L15 1.2 Pin Descriptions SPKTXDAT/ GPIO13 J6 DBVDD I/O Digital speaker (PDM) data output/GPIO/I2C data input and output. GPIO output is selectable CMOS or open drain; SPKTXDAT output is CMOS. PU/PD/K/H/ C/OD GPIO13 input with bus-keeper Supply AGND D3 — — Analog ground (return path for AVDD and MICVDD) — — AVDD D1 — — Analog supply — — CPGND C12 — — Charge pump ground (return path for CPVDD) — — CPVDD C14 — — Supply for charge pump — — DBVDD K11 — — Digital buffer (I/O) supply — — DCVDD K9 — — Digital core supply — — DGND J8 — — Digital ground (return path for DCVDD and DBVDD) — — MICVDD C2 — — Microphone bias supply (input to MICBIAS regulator) — — SPKGNDN K1 — — Speaker driver ground (return path for SPKVDD) 3 —— SPKGNDP H1 — — Speaker driver ground (return path for SPKVDD) 3 —— SPKVDD J4 — — Speaker driver supply — — SUBGND C4 — — Substrate ground — — 1.Note that the default conditions described are not valid if modified by the boot sequence or by a wake-up control sequence. 2.The analog input functions on these pins are referenced to the MICVDD power domain. The digital input/output functions are referenced to the MICVDD or MICBIAS1 power domain, as selected by the IN1_DMIC_SUP field. 3. Separate P/N ground connections are provided for the Class D speaker output, which provides flexible support for current monitoring and output-protection circuits. If this option is not used, these ground connections should be tied together on the PCB. Table 1-1. Pin Descriptions (Cont.) PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain. Pin Name Pin # Power Supply I/O Pin Description Digital Pad Attributes State at Reset 1 |
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