CS47L15 datasheet(87/279 Pages) CIRRUS

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DS1137F2

CS47L15

4.4 DSP Firmware Control

4.4.5

DSP Interrupts

The DSP core provides inputs to the interrupt circuit and can be used to trigger an interrupt event when the associated

conditions occur. The following interrupts are provided for DSP core:

• DMA interrupt—Asserted when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled

DSP output (RDMA) channel buffers have been emptied

• DSP Start 1, DSP Start 2 interrupts—Asserted when the respective start signal is triggered

• DSP Busy interrupt—Asserted when the DSP is busy (i.e., when firmware execution or DMA processes are started)

• DSP Bus Error interrupt—Asserted when a locked register address, invalid memory address, or watchdog timeout

error is detected

The CS47L15 also provides 16 control bits that allow the DSP core to generate programmable interrupt events. When a

1 is written to these bits (see Table 4-32), the respective DSP interrupt (DSP_IRQn_EINTx) is triggered. The associated

interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See Section 4.12 for further details.

R1048112 (0xF_FE30)

DSP1_DMA_Config_1

23:16 DSP1_WDMA_CHANNEL_

ENABLE[7:0]

0x00

DSP1 WDMA Channel Enable

There are eight WDMA channels; each bit of this field enables

the respective WDMA channel.

Each bit is coded as follows:

0 = Disabled

1 = Enabled

13:0 DSP1_DMA_BUFFER_

LENGTH[13:0]

0x0000

DSP1 DMA Buffer Length

Selects the amount of data transferred in each DMA channel.

The LSB represents one 24-bit DSP memory word.

R1048114 (0xF_FE32)

DSP1_DMA_Config_2

7:0

DSP1_WDMA_CHANNEL_

OFFSET[7:0]

0x00

DSP1 WDMA Channel Offset

There are eight WDMA channels; each bit of this field offsets the

start Address of the respective WDMA channel.

Each bit is coded as follows:

0 = No offset

1 = Offset by 0x8000

R1048116 (0xF_FE34)

DSP1_DMA_Config_3

21:16 DSP1_RDMA_CHANNEL_

OFFSET[5:0]

0x00

DSP1 RDMA Channel Offset

There are six RDMA channels; each bit of this field offsets the

start Address of the respective RDMA channel.

Each bit is coded as follows:

0 = No offset

1 = Offset by 0x8000

5:0

DSP1_RDMA_CHANNEL_

ENABLE[5:0]

0x00

DSP1 RDMA Channel Enable

There are six RDMA channels; each bit of this field enables the

respective RDMA channel.

Each bit is coded as follows:

0 = Disabled

1 = Enabled

R1048118 (0xF_FE36)

DSP1_DMA_Config_4

DSP1_DMA_WORD_SEL

DSP1 Data Word Format

0 = Q3.20 format (4 integer bits, 20 fractional bits)

1 = Q0.23 format (1 integer bit, 23 fractional bits)

The data word format should be set according to the

requirements of the applicable DSP firmware.

Table 4-32. DSP Interrupts

Bit

Label

Default

Description

R5632 (0x1600)

ADSP2_IRQ0

DSP_IRQ2

DSP IRQ2. Write 1 to trigger the DSP_IRQ2_EINTn interrupt.

DSP_IRQ1

DSP IRQ1. Write 1 to trigger the DSP_IRQ1_EINTn interrupt.

R5633 (0x1601)

ADSP2_IRQ1

DSP_IRQ4

DSP IRQ4. Write 1 to trigger the DSP_IRQ4_EINTn interrupt.

DSP_IRQ3

DSP IRQ3. Write 1 to trigger the DSP_IRQ3_EINTn interrupt.

Table 4-31. DMA Control (Cont.)

Bit

Label

Default

Description

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