PCA85262 datasheet(36/55 Pages) NXP

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PCA85262

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Product data sheet

Rev. 3 — 12 November 2018

36 of 55

NXP Semiconductors

PCA85262

Automotive 32 x 4 LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to 8 PCA85262 can be recognized on the same I2C-bus

by using the 2-bit hardware subaddress (A0 and A1) and the programmable I2C-bus slave

address (SA0).

When cascaded PCA85262 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85262 of the cascade contribute

additional segment outputs. The backplanes can either be connected together to enhance

the drive capability or some can be left open-circuit (such as the ones from the slave in

Figure 26) or just some of the master and some of the slave can be taken to facilitate the

layout of the display.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85262. Synchronization is guaranteed after a power-on and initialization. The only

time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by

noise in adverse electrical environments or by defining a multiplex drive mode when

PCA85262 with different SA0 levels are cascaded).

Table 20.

Addressing cascaded PCA85262

Cluster

Bit SA0

Pin A1

Pin A0

Device

000

011

102

113

004

015

106

117

PCA85262 Datasheet(PDF) 36 Page - NXP Semiconductors