PCA85262 datasheet(9/55 Pages) NXP

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PCA85262

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Product data sheet

Rev. 3 — 12 November 2018

9 of 55

NXP Semiconductors

PCA85262

Automotive 32 x 4 LCD driver for low multiplex rates

6.3 Display RAM

The display RAM is a static 32

 4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the

segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,

second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,

BP2, and BP3 respectively.

When display data is transmitted to the PCA85262, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment

numeric display showing all drive modes is given in Figure 4; the RAM filling organization

depicted applies equally to other LCD types.

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as four successive 2-bit RAM words

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address, but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 6.3.4)

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 3.

Display RAM bitmap

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