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LTC2873

REV B

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Figure 18. RS485 Receiver Input Threshold Characteristics

with Typical Values Shown

2873 F18

–110mV –70mV

+110mV

A/DO TO B/RI

RISING THRESHOLD

SHIFTS IF SIGNAL IS

IN WINDOW > ~0.7µs

TO SUPPORT

FAILSAFE

TYPICAL APPLICATIONS

RS485 Balanced Receiver with Full Failsafe Operation

The LTC2873 RS485 receiver has a differential threshold

voltage that is about +110mV for signals that are rising

and –110mV for signals that are falling, as illustrated in

Figure18.Ifadifferentialinputsignallingersinthewindow

between these thresholds for more than about 0.7µs, the

rising threshold changes from +110mV to –70mV, while

the falling threshold remains at –110mV. Thus, differential

inputs that are shorted, open, or terminated but not driven

for more than 0.7µs produce a high on the receiver output,

indicating a failsafe condition.

(A-B)

200mV/DIV

5V/DIV

2873 F19

200ns/DIV

Figure 19. A 3Mbps Signal Driven Down 4000ft of

CAT-5e Cable. Top Traces: Received Signals After

Transmission Through Cable; Middle Trace: Math

Showing Differences of Top Two Signals; Bottom

Trace: Receiver Output

The benefit of this dual threshold architecture is that

it supports full failsafe operation yet offers a balanced

threshold, centered on 0V, for normal data signals. This

balance preserves duty cycle for small input signals with

heavily slewed edges, typical of what might be seen at the

end of a very long cable. This performance is highlighted

in Figure 19, where a signal is driven through 4000ft of

CAT-5e cable at 3Mbps. Even though the differential sig-

nal peaks are at only 200mV and is heavily slewed, the

output maintains a nearly perfect signal with almost no

duty cycle distortion.

An additional benefit of the balanced architecture is excel-

lent noise immunity due to the wide effective differential

input signal hysteresis of 220mV for signals transitioning

throughthewindowregioninlessthan0.7µs.Increasingly

slower signals will have increasingly less effective hyster-

esis, limited by the DC failsafe hysteresis of about 40mV.

RS485 Biasing Network Not Required

RS485 networks are often biased with a resistive divider

to generate a differential voltage of ≥200mV on the data

lines, which establishes a logic-high state when all the

transmitters on the network are disabled. The values of

the biasing resistors depend on the number and type

of transceivers on the line and the number and value of

terminating resistors. Therefore, the values of the biasing

resistors must be customized to each specific network

installation, and may change if nodes are added to or

removed from the network.

The internal failsafe feature of the LTC2873 eliminates the

need for external network biasing resistors provided they

are used in a network of transceivers with similar internal

failsafe features. This also allows the network to support

a high number of nodes, up to 256, by eliminating the

bias resistor loading. The LTC2873 transceiver operates

correctly on biased, unbiased, or under-biased networks.

If a twisted pair has unbalanced capacitance from its two

conductors to AC ground, common mode transients can

translate into small differential voltages. If the common

mode event is large and fast enough, the resulting dif-

ferential voltage can cause a receiver, whose inputs are

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