LTC2802 datasheet(23/32 Pages) AD

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LTC2873

REV B

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Figure 23. Cable Length vs Data Rate

(RS485/RS422 Standard Shown in Vertical Dashed Line)

DATA RATE (bps)

2873 F23

10k

100

10k

10M

100M

100k

LTC2873

MAX DATA RATE

RS485/RS422

MAX DATA RATE

cycle distortion, cable properties and data rate. A typical

curve of cable length versus maximum data rate is shown

in Figure 23. Various regions of this curve reflect different

performance limiting factors in data transmission.

At frequencies below 100kbps, the maximum cable length

is determined by DC resistance in the cable. In this ex-

ample, a cable longer than 4000ft will attenuate the signal

at the far end to less than what can be reliably detected

by the receiver.

For data rates above 100kbps, the capacitive and inductive

properties of the cable begin to dominate this relation-

ship. The attenuation of the cable is frequency and length

dependent, resulting in increased rise and fall times at

the far end of the cable. At high data rates or long cable

lengths, these transition times become a significant part

of the signal bit time. Jitter and inter symbol interference

aggravate this so that the time window for capturing valid

data at the receiver becomes impossibly small.

The boundary at 20Mbps in Figure 23 represents the

guaranteed maximum operating rate of the LTC2873. The

dashed vertical line at 10Mbps represents the specified

maximum data rate in the RS485 standard. This boundary

is not a limit, but reflects the maximum data rate that the

specification was written for. It should be emphasized

that the plot in Figure 23 shows a typical relation between

maximum data rate and cable length. Results with the

LTC2873 will vary, depending on cable properties such

as conductor gauge, characteristic impedance, insulation

material, and solid versus stranded conductors.

APPLICATIONS INFORMATION

Layout Considerations

All VCC pins must be connected together and all ground

pins must be connected together on the PC board with

very low impedance traces or dedicated planes. A 2.2µF,

or larger, bypass capacitor should be placed less than

7mm away from VCC Pin 14. This VCC pin, as well as GND

Pin 11, mainly service the DC/DC converter. Additional

bypass capacitors of 0.1µF or larger, can be added from

VCC pin 18 to ground pin 16 if the traces back to the 2.2µF

capacitor are indirect or narrow. These VCC and ground

pins mainly service the RS485 driver. Table 2 summarizes

the bypass capacitor requirements. The capacitors listed

in the table should be placed closest to their respective

supply and ground pin.

Table 2. Bypass Capacitor Requirements

CAPACITOR (µF)

SUPPLY (PIN)

RETURN (PIN)

COMMENT

2.2

VCC (14)

GND (11)

Required

1.0

VDD (13)

GND (11)

Required

1.0

VEE (10)

GND (11)

Required

0.1

VL (22)

GND (20)

Required*

0.1

VCC (18)

GND (16)

Optional

0.1

VCC (21)

GND (20)

Optional

*If VL is not connected to VCC.

Place the charge pump capacitor, C1, directly adjacent to

the SW and CAP pins, with no more than one centimeter

of total trace length to maintain low inductance. Close

placement of the inductor, L1, is of secondary importance

compared to the placement of C1 but should include no

more than two centimeters of total trace length.

The PC board traces connected to high speed bus signals

A/DO and B/RI should be symmetrical and as short as

possible to minimize capacitive imbalance and to maintain

good differential signal integrity. To minimize capacitive

loadingeffects,thedifferentialsignalsshouldbeseparated

by more than the width of a trace and should not be routed

on top of each other if they are on different signal planes.

Care should be taken to route outputs away from any

sensitive inputs to reduce feedback effects that might

cause noise, jitter, or even oscillations. For example, DI,

A/DO, and B/RI should not be routed near RO.

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