LTC3370 datasheet(11/24 Pages) AD

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LTC3315A

Rev. A

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OPERATION

Buck Switching Regulators

The LTC3315A is a 5V dual 2A monolithic, constant fre-

quency, peak current mode step-down DC/DC converter.

The synchronous buck switching regulators are internally

compensated and require only external feedback resistors

to set the output voltage.

An internal oscillator, which can be externally synchro-

nized, turns on the internal PMOS power switch at the

beginning of each clock cycle. Current in the inductor

ramps up until the PMOS current comparator trips and

turns off the PMOS. The peak inductor current, IPEAK, at

which the PMOS turns off is controlled by an internal VC

voltage which the error amplifier regulates by compar-

ing the voltage on the feedback (FB) pin with an internal

500mV reference. An increase in the load current causes

a reduction in the feedback voltage relative to the refer-

ence, causing the error amplifier to raise the VC voltage

(and IPEAK) until the average inductor current matches the

new load current. When the PMOS turns off, the NMOS

turns on and ramps down the inductor current for the

remainder of the clock cycle or, if in pulse skipping mode

or Burst Mode, until the inductor current falls to zero. If

an overload condition results in excessive current flowing

through the NMOS, the next clock cycle will be skipped

until the current returns to a safe level.

Each buck switching regulator has its own SW, FB, and

EN pins. The buck input supplies are internally connected,

but each VIN pin should have its own input bypass capaci-

tor (see Applications Information). The enable pins have

precision 400mV thresholds which may be used to pro-

vide event-based power-up sequencing by connecting

the enable pin to the output of another buck through a

resistor divider. If the EN pin of a buck is low, that buck is

in shutdown and in a low quiescent current state. If both

EN pins are low, both bucks are in shutdown, the SW

pins are high impedance, and the quiescent current of the

LTC3315A is 1µA (typical). If either EN pin is above the

enable threshold of 400mV its respective buck is enabled.

Both buck regulators have forward and reverse inductor

current limiting, soft-start to limit inrush current during

start-up, and short-circuit protection. When both bucks

are disabled and either buck is subsequently enabled,

there is a 400µs (typical) delay while internal circuitry

powers up followed by a 100µs (typical) no start time

before switching commences and the soft-start ramp

begins. If a second buck is then enabled, it will also have

a 100µs (typical) no start time. If the second buck is

enabled within 400µs of the first buck, it will wait until

the expiry of the 400µs to begin its no start time.

The buck switching regulators are switched 180° out of

phase with respect to each other. The phase determines

the fixed edge of the switching sequence, which is when

the PMOS turns on. The PMOS off (NMOS on) phase is

subject to the regulated duty cycle of each buck.

Mode Selection

The buck switching regulators operate in three different

modes set by the MODE/SYNC pin: pulse skipping mode

(when the MODE/SYNC pin is set low), forced continuous

PWM mode (when the MODE/SYNC pin is floating), and

Burst Mode (when the MODE/SYNC pin is set high). The

MODE/SYNC pin sets the operating mode for both buck

switching regulators.

In pulse skipping mode, the oscillator operates continu-

ously and positive SW transitions are aligned to the clock.

Negative inductor current is disallowed and during light

loads switch pulses are skipped to regulate the output.

In forced continuous mode, the oscillator runs continu-

ously, no pulses are skipped, and switching occurs in

every cycle. To maintain regulation, the inductor current

is allowed to reverse under light load conditions. This

mode allows the buck to run at a fixed frequency with

minimal output ripple. In forced continuous mode if the

inductor current reaches –1A (typical, 1A into the SW pin)

the NMOS will turn off for the remainder of the cycle to

limit the current.

In Burst Mode operation, at light loads, the output capaci-

tor is charged to a voltage slightly higher than its regu-

lation point. The regulator then goes into a sleep state,

during which time the output capacitor provides the load

current. In sleep most of the regulator’s circuitry is pow-

ered down, helping to conserve input power. When the

output voltage drops below its programmed value, the cir-

cuitry is powered back on and another burst cycle begins.

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