LTC4232 datasheet(11/22 Pages) AD

11 / 22 page

LTC4231

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

In most applications, keeping the inrush current at ana-

log current limit is an acceptable start-up method if the

TIMER delay is long enough to avoid setting the current

fault latch and the MOSFET has adequate safe operating

margin. However, for more flexibility in design (See the

Design Example section), a capacitor from GATE to GND

(Figure 1) can be used to limit the VGATE slew rate for inrush

current control. VGATE rises with a slope equal to 10μA/CG

(Figure 3). The supply inrush current is then limited to:

IINRUSH =

• 10µA

Once ∆VGATE exceeds ∆VGATE(H), STATUS goes high

impedance. ICC drops from 300µA to 4µA (average) dur-

ing this normal on mode as some circuit blocks are shut

down and the internal charge pump periodically turns on

when ∆VGATE droops by 0.7V or every 15ms, whichever

comes first (Figure 7).

In the back-to-back MOSFET configuration as shown in

Figure 5, SOURCE will also be pulled to GND via the para-

sitic body diode between GATE and SOURCE, cutting off

the load from IN. This configuration is suitable in power

path control and reverse battery protection applications

where IN is likely to go below GND.

In the single MOSFET configuration (Figure 1), the 1mA

pull-down from GATE to GND also discharges the load

capacitor CL to GND once GATE goes below SOURCE.

Overcurrent Fault

The 50mV circuit breaker threshold sets the maximum

load current allowed under steady state conditions.

However, the LTC4231 allows mild overcurrents during

supply or load transients when ∆VSENSE momentarily

exceeds 50mV but stays below the 80mV analog current

limit threshold. For severe overcurrents when ∆VSENSE

exceeds 80mV, the analog current limit amplifier controls

∆VGATE to regulate ∆VSENSE to 80mV. The durations of

these transient overcurrents must be less than the cir-

cuit breaker delay (tCB) which can be adjusted using the

capacitor CT at the TIMER pin.

When ∆VSENSE exceeds 50mV, the LTC4231 goes into

overcurrent mode. CT is charged with a 50μA pull-up.

If the overcurrent is transient and ∆VSENSE goes below

50mV before TIMER reaches 1.193V, the 50μA pull-up

on TIMER switches to a 5μA pull-down. Multiple overcur-

rents with a duty cycle > 10% can thus eventually inte-

grate TIMER to 1.193V. When TIMER reaches 1.193V, the

LTC4231 goes into current fault mode and sets an internal

current fault latch. The external MOSFET will be cut off

by a 1mA pull-down from GATE to GND while STATUS

pull-down is asserted.

The time in which LTC4231 stays in overcurrent mode

before going into current fault mode is called the circuit

breaker delay and is given by:

tCB = CT • 24 [ms/µF]

Figure 3. Inrush Control by Limiting VGATE Slew

GATE

20V/DIV

OUT

20V/DIV

ILOAD

0.5A/DIV

20ms/DIV

4231 F03

START-UP

NORMAL ON

DEBOUNCE

Turn-Off Sequence

The MOSFET switch can be turned off by SHDN going low,

an OV/UV event, an overcurrent setting the current fault

latch or IN dropping below its UVLO voltage. Under any

of these conditions, STATUS pulls low and the MOSFET

is turned off with a 1mA current pulling down from GATE

to GND.

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