10 Power Supply Recommendations

The nominal performance of the INA849 is specified with a supply voltage of ±15 V and midsupply reference

voltage. The device also operates using power supplies from ±4 V (8 V) to ±18 V (36 V) and non-midsupply

reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and

reference voltage are shown in Section 7.6.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

• To avoid converting common-mode signals into differential signals, make sure that both input paths are

symmetrical and well-matched for source impedance and capacitance. Even slight mismatch in parasitic

capacitance at the gain setting pins can degrade CMRR over frequency.

• Place the external gain resistor close to the RG pins to keep the loop inductance as low as possible and to

avoid a potential parasitic coupling path, but also so that capacitance mismatch between the RG pins is

minimized.

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

– Connect low-ESR, 0.1-µF, ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Keep traces as short as possible.

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INA849

SBOS945 – NOVEMBER 2020

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