LTC4255

11

4255f

Normal Power-Up

Using channel 1 as an example, a normal power-up cycle

begins when the switch 1 enable bit (A0) and relay 1 enable

bit (A4) are set high and then latched into the chip by a

STOP bit on the serial interface (point A, Figure 9).

The RELAY1 output turns on immediately and energizes

an optional relay connecting the AGND and OUT1 pins to

the GATE1 pin will start to pull high (point B). When the

threshold voltage of the FET is reached, current will begin

flowing in the external FET (point C). The voltage at the

OUT1 pin will then fall at a rate determined by the current

limit and the output load capacitance. Because the current

limit is lower when the OUT1 pin is near AGND due to the

foldback circuit, the voltage will fall slowly at first, then get

faster. At the same time, the current limit timer will start.

The OUT1 voltage must reach its final value and the analog

current limit circuit must turn off before the current limit

timer expires, or a current limit fault will be detected and

the FAULT pin will be pulled low.

APPLICATIO S I FOR ATIO

Figure 9. Normal Power-Up and Power-Down Sequence on Channel 1

(C0) bit will be set (point D) and the open-circuit enable

delay timer started. As long as the load current turns on

before the open-circuit enable delay timer expires, the

FAULT pin will remain in a high impedance state and the

current limit fault status bit (D0) and open-circuit fault

status bit (D4) bits will remain low, thus completing a

normal power-up sequence. The Power_OK bit will re-

main high until the switch is turned off by setting the

switch enable bit (AO) low or a short-circuit or open-

circuit condition turns off the switch.

A normal power-down sequence begins when the switch

enable bit (A0) and relay enable bit (A4) are cleared and

then latched into the chip by a STOP bit on the serial

interface (point E). The RELAY1 pin will go into a high

impedance state and the inductive voltage spike from the

primary coil will be clamped at about 18V. The relay will

typically disengage several milliseconds later. At the same

time, the GATE1 pin will be pulled low by a 50

µA current

source, the FET will turn off, and the Power_OK bit will be

cleared.

AO

ACK

AO

ACK

STOP BIT

SCL

SDA

SHORT-CIRCUIT STATUS

(D0)

OPEN-CIRCUIT STATUS

(D4)

POWER_OK

(C0)

FAULT

RELAY1

GATE1

OUT1

AB

C

D

E

FET TURNS ON

POWER OK

4255 F09