LTC4255 datasheet(12/16 Pages) LINER

12 / 16 page

LTC4255

4255f

open-circuit fault status bit (D4) will be set (point E). The

FAULT pin will pull low to generate an interrupt to the

processor which can then read the status register to

determine which channel faulted.

When the fault clear bit (B0) is set during a write cycle via

the 2-wire interface (point F), the FAULT pin goes into a

high impendance state, the open-circuit fault status bit

(D4) is cleared, and the channel is allowed to turn back on

if the relay 1 enable (A4) and switch 1 (AO) enable bits are

set (point G.)

The channel is always turned off after an open-circuit fault

detection and not allowed to automatically restart.

Power-Up with No Load

When a channel powers-up with no load, the initial

sequence is the same as the normal case. When the VOUT1

voltage is within the power good threshold, the Power_OK

bit is set (point D, Figure 10) and the open-circuit enable

delay timer started. The duration of the timer can be

programmed via bits B6-B7.

When the open-circuit enable timer expires (tOCD, point E),

the open-circuit detector is enabled if the global open-

circuit detect enable bit (B2) has been set. When the

voltage across the sense resistor is less than 3mV(typ) for

at least 18ms (tOCF), the FET will be turned off, and the

Figure 10. Power-Up Sequence with No Load on Channel 1

APPLICATIO S I FOR ATIO

4255 F10

ACK

STOP BIT

SCL

SDA

SHORT-CIRCUIT STATUS

(D0)

OPEN-CIRCUIT STATUS

(D4)

POWER_OK

(C0)

FAULT

RELAY1

GATE1

OUT1

FET TURNS ON

POWER OK

tOD

tOCD

OPEN CIRCUIT

TIMER EXPIRES

OPEN CIRCUIT

DETECTED

FAULT CLEARED

LTC4255 Datasheet(PDF) 12 Page - Linear Technology

LTC4255 Datasheet(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL