ZSSC3123AI2R datasheet(16/67 Pages) RENESAS

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ZSSC3123 Datasheet

August 16, 2018

9. Circuit Description

9.1

Signal Flow and Block Diagram

As seen in the following figure, the ZSSC3123 comprises three main blocks: the analog core, digital core, and output communication. The

capacitive input is first sampled by the analog core using a charge-balancing CDC and is adjusted for the appropriate capacitance range using

the CDC_Offset, CDC_Reference, and CDC_Mult settings. The digital core corrects the digital sample with an on-chip digital signal processor

(DSP), which uses coefficients stored in EEPROM for precise conditioning. An internal temperature sensor can be used to compensate for

temperature effects of the capacitive input. A temperature value can also be calibrated and output as a 14-bit reading.

The corrected capacitance value can be read using four different output types, I2C, SPI, PDM, and alarms. They can all be directly interfaced

with a microcontroller, and optional filtering of the PDM output can provide a ratiometric analog output. The alarm pins can also be used to

control a variety of analog circuitry.

Figure 9. ZSSC3123 Block Diagram

ZSSC3123 cLite Capacitive Sensor Signal Conditioner

Digital Core

Analog Core

Sensor

(Optional)

Output

Communication

MUX

VSS

VDD (2.3V to 5.5V)

Temp

Sensor

CLK/Reset

C/A

CDC

Ref

Cap

Offset

Cap

SCL/SCLK

SDA/MISO

Ready/PDM_C

Alarm_Low/PDM_T

Alarm_High

Ready

PDM

I2C / SPI

Low Alarm

High Alarm

EEPROM

ROM

DSP

0.1µF

Vcore

9.2

Analog Front End

9.2.1 Capacitance-to-Digital Converter

A 1st-order charge-balancing capacitance-to-digital converter (CDC) is used to convert the input capacitance to the digital domain. The CDC

uses a chopper-stabilized design to decrease any drift over temperature. The CDC interfaces to the sensor capacitor through the input

multiplexer that controls whether the measurement is a capacitance or a temperature measurement. The input multiplexer also allows for two

sensor capacitance configurations: a single-sensor capacitance or a two-sensor, ratio-based differential capacitance configuration, where the

reference capacitor is part of the sensor.

As part of a switched-capacitor network, the reference capacitor C1 is driven by a square-wave voltage of the frequency fEXC (see section 5).

The sensor capacitance C0 is not exposed to DC voltages in order to prevent the aging effects of some sensor types. The configuration of the

CDC is controlled by programming settings in EEPROM word C_Config. (See Table 30 for settings.)

ZSSC3123AI2R Datasheet(PDF) 16 Page - Renesas Technology Corp

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