F0440 Datasheet

© 2020 Renesas Electronics Corporation

6

August 13, 2020

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Serial Clock Speed

10

MHz

CSb_A, CSb_B to first serial

clock rising edge

A

SPI 3 wire Bus. 50% of CSb falling

edge to 50% of CLK rising edge.

10

ns

Serial Data Hold Time

B

SPI 3 wire Bus. 50% of CLK rising

edge to 50% of Data falling edge.

10

ns

Final serial clock rising edge to

CSb

C

SPI 3 wire Bus. 50% of CLK rising

edge to 50% of CSb rising edge.

10

ns

DSA0 Phase Settling Time

value, 0 dB state to 6 dB state

24

35

ns

value, 6 dB state to 0 dB state

18

35

ns

a. Items in min/max columns in bold italics are Guaranteed by Test.

b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.

c. During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up.

d. Time for the gain to settle within ± 0.1 dB and relative to SPI command latch.