VSC8221 datasheet(57/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

57 of 60

19 EEPROM INTERFACE

The EEPROM interface consists of the EEDAT and EECLK pins of the PHY. if this interface is used, these pins should connect

to the SDA and SCL pins respectively of a serial EEPROM that is compatible with the AT24xxx series of ATMEL EEPROMs.

The EEPROM interface on the VSC8221 serves the following purposes:

• it provides the PHY with the ability to self configure its internal registers.

• The system manager can access the EEPROM to obtain information pertaining to the system/module configuration.

• A single EEPROM can be shared among multiple PHYs for their custom configuration.

The PHY detects the EEPROM based on the presence of a pullup on the EEDAT pin. it is initialized using the configuration

EEPROM (if present) under the following conditions:

• RESET deassertion.

• TXDiS/SRESET deassertion and Extended Mii Register 21E.14 is set.

• S/W reset (Mii Register 0.15) is asserted and Extended Mii Register 21E.14 is set.

if an EEPROM is present, the start-up control block looks for a “Microsemi Header” (value:16’hBDBD’) at address 0 and 1 of the

EEPROM. The address is incremented by 256 until the Microsemi Header is found. if the Microsemi Header is not found, or no

EEPROM is connected, the VSC8221 bypasses the EEPROM read step.

Once the Microsemi header is located, the EEPROM interface block of the PHY searches for its PHY address in bit position 7:3

in the subsequent EEPROM location. Once the PHY address is located, the 11 bit EEPROM address location for the start of the

configuration script is read. At this point, the PHY begins reading from this 11 bit EEPROM address and initializes its Register

values based on the EEPROM configuration script contents. Refer to Table 28: “Configuration EEPROM Data Format” for

details on the configuration EEPROM data format.

The total number of EEPROM bytes needed for a configuration script is equal to:

((Number of Register writes) * 3 + 2 (BDBD) + 2 (PHY address and Configuration Script Address) + 2 (Length of configuration

script)).

Data is read from the EEPROM sequentially (at 50 Khz, or 50 kbits/s) until all PHY registers are set. Once all of the PHY

registers are set, the PHY enters the ‘NORMAL STATE’. For more information, see Section 20 on page 61.

if the PHY is in the ‘NORMAL STATE’ state, the user can access the EEPROM connected to the EEPROM interface through the

SMi. if the SMi is in iEEE mode, the EEPROM can be accessed via the SMi using Extended Mii Registers 21E and 22E. if the

SMi is in MSA mode, the EEPROM can be accessed directly via the SMi i.e. the PHY behaves as if the MODDEF2 and

MODDEEF1 pins of the SMi are directly connected to the EEDAT and EECLK pins of the PHY.1

One exception is the memory portion with device/page address ‘110’. This is reserved for the PHY Register access when the

PHY’s SMi is set in MSA mode.

if an EEPROM is present, but the EEPROM does not acknowledge (according to the ATMEL EEPROM protocol), the VSC8221

waits for an acknowledgement for approximately 3 seconds. if there is no acknowledgement within 3 seconds, the VSC8221 will

abort and continue into normal operation.

19.1 Programming Multiple VSC8221s Using the Same EEPROM

To prevent contention on the 2 wire bus when multiple PHYs use the same EEPROM for initialization, the EEPROM start-up

block of each VSC8221 monitors the bus for (PHY Address[4:0] + 1) * 9 + 92 clock cycles for no bus activity and only then

attempts to access the EEPROM bus. PhyAddress[4:0] is chosen because these are the PHY Address bits that are unique to

each VSC8221 (that is, VSC8221 with lowest PHY Address gets priority in this bus).

1EEPROM memory with device address ‘110’ cannot be accessed directly when the SMi is in MSA mode. This device address is reserved for

PHY Register access in MSA mode. To access an EEPROM with device address ‘110’ in MSA mode, Extended Mii Registers 21E and 22E

should be used.

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