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ADRV9029BBCZ Datasheet(PDF) 13 Page - Analog Devices |
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ADRV9029BBCZ Datasheet(HTML) 13 Page - Analog Devices |
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13 / 133 page  Data Sheet ADRV9029 Rev. 0 | Page 13 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments AUXILIARY SYNTHESIZER LO3 Frequency Step 1.8 Hz 1.625 GHz to 3.25 GHz, 61.44 MHz PFD frequency Spectral Purity −65 dBc |fRFLO − fAUXLO| > 15 MHz Integrated Phase Noise Integrated from 1 kHz to 100 MHz, PLL bandwidth optimized for integrated phase noise 800 MHz LO3 0.18 °rms 1800 MHz LO3 0.22 °rms 2600 MHz LO3 0.46 °rms 3800 MHz LO3 0.43 °rms 4800 MHz LO3 0.70 °rms 5700 MHz LO3 1.12 °rms Spot Phase Noise 800 MHz LO3 100 kHz Offset −112 dBc/Hz 1 MHz Offset −121 dBc/Hz 10 MHz Offset −141 dBc/Hz 1800 MHz LO3 100 kHz Offset −110 dBc/Hz 1 MHz Offset −120 dBc/Hz 10 MHz Offset −134 dBc/Hz 2600 MHz LO3 100 kHz Offset −103 dBc/Hz 1 MHz Offset −114 dBc/Hz 10 MHz Offset −132 dBc/Hz 3800 MHz LO3 100 kHz Offset −104 dBc/Hz 1 MHz Offset −114 dBc/Hz 10 MHz Offset −128 dBc/Hz 4800 MHz LO3 100 kHz Offset −100 dBc/Hz 1 MHz Offset −110 dBc/Hz 10 MHz Offset −127 dBc/Hz 5700 MHz LO3 100 kHz Offset −95 dBc/Hz 1 MHz Offset −106 dBc/Hz 10 MHz Offset −126 dBc/Hz LO PHASE SYNCHRONIZATION Initial Phase Sync Accuracy 0.9 ps CLOCK SYNTHESIZER 4915.2 MHz Sample Clock Integrated Phase Noise 0.69 °rms 1 kHz to 10 MHz, PLL bandwidth optimized for integrated phase noise Spot Phase Noise PLL bandwidth optimized for integrated phase noise 100 kHz Offset −96 dBc/Hz 1 MHz Offset −113 dBc/Hz 10 MHz Offset −140 dBc/Hz 3932.16 MHz Sample Clock Integrated Phase Noise 0.89 °rms 1 kHz to 10 MHz, PLL bandwidth optimized to minimize phase noise at offsets >200 kHz |
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