ATMEGA640 datasheet(254/436 Pages) MICROCHIP

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254

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Mas-

ter. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call

address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledge-

ment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the

general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will oper-

ate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received,

the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the

appropriate software action. The appropriate action to be taken for each status code is detailed in Table 24-4 on

page 255. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode

(see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next

received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA

is zero, the TWI does not acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored and

address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to tem-

porarily isolate the TWI from the 2-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the inter-

face can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as

a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up

and until the TWINT Flag is cleared (by writing it to one). Further data reception will be carried out as normal, with

the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be

held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when

waking up from these Sleep modes.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

ATMEGA640 Datasheet(PDF) 254 Page - Microchip Technology