ATMEGA640 datasheet(257/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Mas-

ter. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call

address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledge-

ment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the

general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will oper-

ate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received,

the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the

appropriate software action. The appropriate action to be taken for each status code is detailed in Table 24-5. The

Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state

0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or

state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final

byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer.

Thus the Master Receiver receives all “1” as serial data. State 0xC8 is entered if the Master demands additional

data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting

NACK from the Master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still

monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may

be used to temporarily isolate the TWI from the 2-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the inter-

face can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as

a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake

up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out as normal,

with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line

may be held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when

waking up from these sleep modes.

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

Table 24-5.

Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler

Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA

STO

TWIN

TWE

0xA8

Own SLA+R has been received;

ACK has been returned

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

0xB0

Arbitration lost in SLA+R/W as

Master; own SLA+R has been re-

ceived; ACK has been returned

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

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