ATMEGA640 datasheet(261/436 Pages) MICROCHIP

261 / 436 page

261

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

24.9 Register Description

24.9.1

TWBR – TWI Bit Rate Register

• Bits 7:0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which gen-

erates the SCL clock frequency in the Master modes. See “Bit Rate Generator Unit” on page 242 for calculating bit

rates.

24.9.2

TWCR – TWI Control Register

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by

applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to

control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write

collision if data is attempted written to TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application software response. If

the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag

is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it.

Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that

clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is

generated on the TWI bus if the following conditions are met:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily.

Address recognition can then be resumed by writing the TWEA bit to one again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI

hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the

bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to

claim the bus Master status. TWSTA must be cleared by software when the START condition has been

transmitted.

Bit

76543210

(0xB8)

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

TWBR1

TWBR0

TWBR

Read/Write

R/W

Initial Value

00000000

Bit

76543210

(0xBC)

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

TWCR

Read/Write

R/W

Initial Value

00000000

ATMEGA640 Datasheet(PDF) 261 Page - Microchip Technology

ATMEGA640 Datasheet(HTML) 261 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL