ATMEGA640 datasheet(263/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

To calculate bit rates, see “Bit Rate Generator Unit” on page 242. The value of TWPS1:0 is used in the equation.

24.9.4

TWDR – TWI Data Register

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last

byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt

Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first inter-

rupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus

is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a

sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitra-

tion, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the

TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7:0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial

Bus.

24.9.5

TWAR – TWI (Slave) Address Register

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the

TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In

multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address

comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a

match is found, an interrupt request is generated.

• Bits 7:1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

Bit

76543210

(0xBB)

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

TWDR

Read/Write

R/W

Initial Value

11111111

Bit

76543210

(0xBA)

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

TWAR

Read/Write

R/W

Initial Value

11111110

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