ATMEGA640 datasheet(267/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization

introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and

ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI

is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by

writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is

activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog

Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making

the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt.

When written logic zero, no connection between the Analog Comparator and the input capture function exists. To

make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings

are shown in Table 25-2.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt

Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.

25.2.3

DIDR1 – Digital Input Disable Register 1

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Reg-

ister bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the

digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig-

ital input buffer.

Table 25-2.

ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

Bit

543

210

(0x7F)

–

AIN1D

AIN0D

DIDR1

Read/Write

RRR

R/W

Initial Value

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