ATMEGA640 datasheet(271/436 Pages) MICROCHIP

271 / 436 page

271

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is

cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can

also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,

independently of how the conversion was started.

26.4 Prescaling and Conversion Timing

Figure 26-3. ADC Prescaler

By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz. If

a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be as high as 1000kHz to get a

higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU fre-

quency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the

moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as

the ADEN bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the follow-

ing rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in

ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage to stabi-

lize. If not stabilized, the first value read after the first conversion may be wrong.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC

clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC

Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may

then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from

the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles

after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization

logic.

In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC

remains high. For a summary of conversion times, see Table 26-1 on page 273.

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

Reset

ADEN

START

ATMEGA640 Datasheet(PDF) 271 Page - Microchip Technology