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ATMEGA640 Datasheet(PDF) 286 Page - Microchip Technology |
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ATMEGA640 Datasheet(HTML) 286 Page - Microchip Technology |
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286 / 436 page ![]() 286 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 26.8.4 ADCL and ADCH – The ADC Data Register 26.8.4.1 ADLAR = 0 26.8.4.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 280. Bit 151413 1211 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 76 54 32 10 Read/Write RRR RR RR R RRR RR RR R Initial Value 0 0 0 0 0 0 0 0 00 00 00 00 Bit 151413 1211 10 9 8 (0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH (0x78) ADC1 ADC0 – – – – – – ADCL 76 54 32 10 Read/Write RRR RR RR R RRR RR RR R Initial Value 0 0 0 0 0 0 0 0 00 00 00 00 |
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