ATMEGA640 datasheet(290/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 27-1. Block Diagram

27.3 TAP - Test Access Port

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the

Test Access Port – TAP. These pins are:

•

TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine

•

TCK: Test Clock. JTAG operation is synchronous to TCK

•

TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains)

•

TDO: Test Data Out. Serial output data from Instruction Register or Data Register

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in

reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-

scan and programming. The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debug-

ger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the whole

system, assuming only open collectors on the reset line are used in the application.

TAP

CONTROLLER

TDI

TDO

TCK

TMS

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT

FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock lines

DEVICE BOUNDARY

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