ATMEGA640 datasheet(293/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

execution of Assembly programs assembled with Microchip’s AVR MCU Assembler and C programs compiled with

third party vendors’ compilers.

AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT.

For a full description of the AVR Studio, refer to the AVR Studio User Guide. Only highlights are presented in this

document.

All necessary execution commands are available in AVR Studio, both on source level and on disassembly level.

The user can execute the program, single step through the code either by tracing into or stepping over functions,

step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execu-

tion, and reset the execution target. In addition, the user can have an unlimited number of code Break Points (using

the BREAK instruction) and up to two data memory Break Points, alternatively combined as a mask (range) Break

Point.

27.6 On-chip Debug Specific JTAG Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within Microchip and to

selected third party vendors only. Instruction opcodes are listed for reference.

27.6.1

PRIVATE0; 0x8

Private JTAG instruction for accessing On-chip debug system.

27.6.2

PRIVATE1; 0x9

Private JTAG instruction for accessing On-chip debug system.

27.6.3

PRIVATE2; 0xA

Private JTAG instruction for accessing On-chip debug system.

27.6.4

PRIVATE3; 0xB

Private JTAG instruction for accessing On-chip debug system.

27.7 Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are

the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not

required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register

must be cleared to enable the JTAG Test Access Port.

The JTAG programming capability supports:

•

Flash programming and verifying

•

EEPROM programming and verifying

•

Fuse programming and verifying

•

Lock bit programming and verifying

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the

OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no

back-door exists for reading out the content of a secured device.

The details on programming through the JTAG interface and programming specific JTAG instructions are given in

the section “Programming via the JTAG Interface” on page 342.

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