ATMEGA640 datasheet(291/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 27-2. TAP Controller State Diagram

27.3.1

TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry,

JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 27-2 depend on

the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The ini-

tial state after a Power-on Reset is Test-Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

•

At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register

– Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction Register

from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in

order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting

TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the

TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls

the circuitry surrounding the selected Data Register.

•

Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel

output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only

used for navigating the state machine.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

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