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ATMEGA640 Datasheet(PDF) 363 Page - Microchip Technology |
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ATMEGA640 Datasheet(HTML) 363 Page - Microchip Technology |
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363 / 436 page  363 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATme- ga640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400kHz) with other ATmega640/1280/1281/2560/2561 devices, as well as any other device with a proper tLOW acceptance margin. Figure 31-6. 2-wire Serial Bus Timing 31.7 SPI Timing Characteristics See Figure 31-7 and Figure 31-8 on page 364 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz tSU;STA tLOW tHIGH tLOW tof tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL SDA tr Table 31-8. SPI Timing Parameters Description Mode Min. Typ. Max. 1 SCK period Master See Table 21-5 on page 198 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1600 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 |
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