ATMEGA640 datasheet(367/436 Pages) MICROCHIP

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367

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Note:

Values are guidelines only.

31.9 External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

Conversion Time

260

µs

AVCC

Analog Supply Voltage

VCC - 0.3

VCC + 0.3

VREF

Reference Voltage

2.7

AVCC - 0.5

VIN

Input Voltage

GND

VCC

VDIFF

Input Differential Voltage

-VREF/Gain

VREF/Gain

ADC Conversion Output

-511

511

LSB

Input Bandwidth

4kHz

VINT

Internal Voltage Reference

2.3

2.56

2.8

RREF

Reference Input Resistance



RAIN

Analog Input Resistance

100



Table 31-11. External Data Memory Characteristics, 4.5 to 5.5 Volts, No Wait-state

Symbol

Parameter

8MHz Oscillator

Variable Oscillator

Unit

Min.

Max.

Min.

Max.

01/tCLCL

Oscillator Frequency

0.0

MHz

1tLHLL

ALE Pulse Width

115

1.0tCLCL-10

2tAVLL

Address Valid A to ALE Low

57.5

0.5tCLCL-5

(1)

tLLAX_ST

Address Hold After ALE Low,

write access

tLLAX_LD

Address Hold after ALE Low,

read access

4tAVLLC

Address Valid C to ALE Low

57.5

0.5tCLCL-5(1)

5tAVRL

Address Valid to RD Low

115

1.0tCLCL-10

6tAVWL

Address Valid to WR Low

115

1.0tCLCL-10

7tLLWL

ALE Low to WR Low

47.5

67.5

0.5tCLCL-15(2)

0.5tCLCL+5(2)

8tLLRL

ALE Low to RD Low

47.5

67.5

0.5tCLCL-15

(2)

0.5tCLCL+5

(2)

9tDVRH

Data Setup to RD High

tRLDV

Read Low to Data Valid

1.0tCLCL-50

tRHDX

Data Hold After RD High

tRLRH

RD Pulse Width

115

1.0tCLCL-10

tDVWL

Data Setup to WR Low

42.5

0.5tCLCL-20(1)

tWHDX

Data Hold After WR High

115

1.0tCLCL-10

tDVWH

Data Valid to WR High

125

1.0tCLCL

tWLWH

WR Pulse Width

115

1.0tCLCL-10

Table 31-10. ADC Characteristics, Differential Channels (Continued)

Symbol

Parameter

Condition

Min. (1)

Typ. (1)

Max. (1)

Unit

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