1.8V, 12-Bit, 170Msps ADC for

Broadband Applications

4

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LVCMOS DIGITAL INPUTS (CLKDIV,

T/B)

Digital Input Voltage Low

V

Digital Input Voltage High

V

TIMING CHARACTERISTICS

CLK-to-Data Propagation Delay

Figure 4

1.75

ns

CLK-to-DCLK Propagation Delay

Figure 4

4.95

ns

DCLK-to-Data Propagation Delay

2.8

3.2

3.6

ns

LVDS Output Rise Time

460

ps

LVDS Output Fall Time

460

ps

Output Data Pipeline Delay

Figure 4

11

Clock

cycles

POWER REQUIREMENTS

Analog Supply Voltage Range

1.70

1.80

1.90

V

Digital Supply Voltage Range

1.70

1.80

1.90

V

Analog Supply Current

375

425

mA

Digital Supply Current

63

75

mA

Analog Power Dissipation

788

900

mW

Offset

1.8

mV/V

Power-Supply Rejection Ratio

(Note 4)

PSRR

Gain

1.5

%FS/V

Note 1:

≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.

Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-

scale range (FSR) is defined as 4095 x slope of the line.

Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.